1. Field of the Invention
The present invention relates to a signal processing part of a digital-signal-processing camera.
2. Discussion of the Prior Art
In recent years, many digital-signal-processing cameras have been developed. Hereinafter, an example of the above-mentioned conventional digital-signal-processing camera is described with reference to the drawings.
FIG. 7 is a block diagram showing a construction of the conventional digital-signal-processing camera. In FIG. 7, numeral 51 designates a solid-state image-pickup element; numeral 52 designates a drive circuit which drives the solid-state image-pickup element 51 so that the solid-state image-pickup element 51 can issue an output signal prior to an end time of horizontal blanking period by a time period T.sub.A (approx. 1 .mu.sec) within a horizontal blanking period; numeral 53 designates a synchronizing signal generation circuit which generates a synchronizing signal; numeral 54 designates a digital-signal-processing circuit which processes output signals of the solid-state image-pickup element 51; numeral 55 designates a picture signal output of the digital-signal-processing circuit 54; numeral 56 designates a synchronizing signal which is generated by the synchronizing signal generation circuit 53.
FIG. 6 shows a construction of a digital filter in the digital-signal-processing circuit. Numeral 61 designates delay elements; numeral 62 designates multipliers; numeral 63 designates an adder.
Operation of the conventional digital-signal-processing camera as constructed above is described hereafter.
First, having a synchronism with the synchronizing signal 56 generated by the synchronizing signal generation circuit 53, the drive circuit 52 generates drive pulses for solid-state image-pickup element to drive the solid-state image-pickup element 51, so that the solid-state image-pickup element 51 issues an output signal prior to an end time of horizontal blanking period by a time period T.sub.A (approx. 1 .mu.sec) within a horizontal blanking period. The digital-signal-processing circuit 54 makes signal processings such as low-pass filter, edge-emphasizing filter and noise reduction filter on the output signal issued from the solid-state image-pickup element 51, and issues as the picture signal 55. Further, the synchronizing signal 56, which has been generated in the synchronizing signal generation circuit 53, is issued together with the picture signal. The digital signal-processing circuit 54 is thus composed of several digital filters. As shown in FIG. 6 (e.g., "Digital Filter" of the seventh chapter of "Digital-signal-processing of picture" by Takahiko FUKINUKI, published by NIKKAN KOGYO SHINBUNSHA), a digital filter is composed of the delay elements 61, the multipliers 62 and the adder 63.
According to such a construction as this, an input signal is delayed through the delay elements 61 of M steps, and turns into an output signal. For example, to have total 100 steps delay elements of the digital filter in the digital-signal-processing circuit with an operation of a clock of 10 MHz is to issue a picture output signal with a delay time of T.sub.B (10 .mu.sec). Therefore, the picture output signal shall be delayed by a time (approx. 9 .mu.sec) of (T.sub.B -T.sub.A) from the horizontal blanking period.
In the above-mentioned construction, the conventional analogue-signal-processing has a delay time of only about 1 .mu.sec and hence delay of a picture signal, which is within the horizontal blanking period, causes no trouble; whereas the digital-signal-processing circuit consists of the digital adder and multiplier and the delay elements, and the digital-signal-processing realized by the whole 100 steps of delay elements generates a delay time of about 10 .mu.sec even when it is driven by a clock of 10 MHz. FIG. 3 is a signal chart of the digital-signal-processing camera, wherein there is a problem that the horizontal blanking signal A and the picture signal D are overlapped each other as shown in FIG. 3. Further, when it is intended that the horizontal synchronizing signal B and the horizontal blanking signal A are made to have a delay time of about 10 .mu.sec, which arises in the digital-signal-processing circuit, by the solid-state image-pickup element and the drive circuit so as to timely match the horizontal synchronizing signal F and the horizontal blanking signal E with the picture signal D, there arises no problem in the horizontal blanking signal E because it is not used to drive the solid-state image-pickup element and is therefore disposed away from the solid-state image-pickup element and the drive circuit so as not to give a disturbance; but the horizontal synchronizing signal F, which is used to drive the solid-state image-pickup element, gives a disturbance to the output signal C of the solid-state image-pickup element, disabling use of the picture signal.